Recent News Design Verity-Check 2.0 is now available: Major improvements in Design Verity-Check include: support for the Accellera PSL (Sugar) property specification language, embedded Verilog assertions, formal clock domain boundary checking and support for user specified rules
. Verity-Check is now available in Japan:
Veritable partners with Japanese Distributor Interlink
to offer Design Verity-Check
in Japan. Interested in the latest developments in verification and test? Check out the Calendar, for upcoming test
and verification events, and our Press Release and
News pages. 
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