Verity-Check Designer:
a formal predictive lint checker Verity-Check Designer, the Design Verity lint and rule checker, is an innovative
predictive RTL analysis tool that simplifies and speeds up design checking using a combination of formal and structural analysis. Detect clock domain synchronization errors Verity-Check Designer supports
multiple clock designs. Formal clock domain boundary checking ensures that data that crosses clock domain boundaries is synchronized. Verity-Check Designer recognizes double register buffering,
memory/register file and customized synchronization schemes. For custom schemes, you can specify allowed synchronization cells. Verity-Check also identifies data that is generated and consumed by different
edges of the same clock and checks for the appropriate use of lock-up latches. Detect races before simulation
Race conditions are a major cause of critical design errors that can take significant amounts of time and effort to debug.
Verity-Check's powerful static analysis techniques reduce design debug time and effort by detecting potential race conditions before simulation and synthesis.Verity-Check identifies race conditions, such
as write-write, read-write, and combinational loop races, and automatically pin-points the lines of source code that are the cause of the race conditions. Automatically check design re-usability Verity-Check includes the
following types of traditional built-in rules checks: Reuse Methodology Manual (RMM), coding style, design for testability (DFT), simulation, synthesis, syntax, and lint. These checks help you catch
errors before you get to simulation and synthesis, and provide a way of ensuring that design teams follow a consistent design style and methodology that enables design re-use. In addition, Verity-Check
allows user-defined checks making it easy for you to add your own rules and messages to its already extensive library of built-in checks. Enforce your design methodology Verity-Check's support for user re-configurable
rules and rule packages allows you to customize rule packages that address your design checking requirements. Predefined packages simplify the enforcement of design methodologies such as design for
re-usability, design for testability and design for verifiability. You can also add your own rules using Perl.
Find design for testability errors at RTL stage Verity-Check allows you to check that your RTL complies with design for
testability (DFT) rules so reducing the amount of time and effort spent at the gate level finding and fixing scan DFT violations. Eliminate design errors earlier Verity-Check eliminates complex design errors at
all stages of your design implementation cycle from RTL to gate level, from module level to full chip. Deploy Verity-Check early in your design cycle to drastically reduce the amount of effort you spend
finding bugs later using time-consuming traditional test-bench methods |
