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Company overview.

Solutions
Lint, Predictive RTL Analysis, Rule Checking, Property Checking , Assertion Based Verification, Automatic Formal Test-bench Generation

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Let Veritable's consultants  solve your toughest SOC design, verification and test problems.

What's New
Check out the latest news in verification and test.

Welcome...
 

provides design verification and test  solutions and services to the electronic design industry. .

Design Verity-Check 2.0 is now available

Major improvements in Design Verity-Check 2.0   include support for: Accellera Property Specification Language (PSL / Sugar), embedded Verilog assertions,  formal clock domain boundary checking, RT level Design For Testability (DFT) rule checking, waveform viewing, an integrated Tcl interpreter and support for user specified rules.

Press Articles

Vendors push for assertion standards

Accellera selects Sugar PSL

Leading Companies Support PSL

Assertion based verification

EE Design Primer

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Verity-Check Designer

Predictive RTL analysis